1. Technical Field
The invention relates to a bipolar transistor with raised base connection region and a process for the production thereof.
2. Discussion of Related Art
Bipolar transistors are used in many different ways in integrated analog and digital electronic circuits. In particular, bipolar transistors are used for high-speed uses because of their short switching times. It was possible to considerably increase the operational efficiency of bipolar transistors in the high-speed area by vertical and lateral scaling of the transistor dimensions and by the introduction of epitaxially produced base layers.
In particular the development of heterobipolar transistors contributed to that. In heterobipolar transistors the emitter and base layers comprise different semiconductor materials, the emitter having a larger band gap than the base. An example in that respect is SiGe-heterobipolar transistors in which the emitter comprises silicon (Si) and the base contains a silicon-germanium alloy (SiGe).
The high frequency properties of modern bipolar transistors are limited in the case of increasing scaling by the resistances of base, emitter and collector as well as parasitic base-emitter and base-collector capacitances. In particular the limit frequency of power amplification can be increased by a reduction in the base resistance. That limit frequency is referred to as fmax. In addition a reduction in the base resistance results in an improvement in the noise properties of the transistor.
The conventional way of reducing base resistance is ion implantation in the extrinsic base region which hereinafter is also referred to as the outer base portion or the outer base region (English term: extrinsic base region). Transistors produced in that way suffer from the disadvantage that implantation damage which occurs in the ion implantation procedure results in increased diffusion of the doping atoms and as a result ultimately limits the operational efficiency of the transistors. FIG. 1 shows the extrinsic and intrinsic base regions in a plan view on to a bipolar transistor.
An alternative concept for reducing base resistance while avoiding implantation damage is to reinforce the base layer by an additional semiconductor layer in the outer base portion. In accordance with the known state of the art, there are two alternative approaches for implementing such reinforced base connection layers:
(1) Production processes which are based on selective epitaxy of the inner base layer portion. The inner base layer portion, hereinafter also referred to as the intrinsic base layer, intrinsic base region or intrinsic base area, forms the region of the base which is arranged in the lateral region of the emitter window therebeneath. Production processes involving selective epitaxy usually employ a polysilicon layer produced prior to deposit of the inner base portion, as the base connection. A transistor of that kind was described by Yamazaki in U.S. Pat. No. 5,523,606. Selective epitaxy is used to deposit a base layer on exposed parts of the substrate surface and in cavities which are formed by the substrate surface and overhangs of the polysilicon layer serving as the base connection. A substantial disadvantage of that structure is poor process control for selective deposit beneath the overhanging polysilicon layer. In addition deposit of the intrinsic base beneath the overhanging base connection layer leads to an increase in the area of the base-collector junction, whereby base-collector capacitance is increased. Those structural limitations ultimately result in a limitation in the high frequency parameters.
(2) Ahlgren et al, U.S. Pat. No. 6,492,238, describe the production of a raised base connection region by means of chemical-mechanical polishing (CMP). The corresponding transistor structure is diagrammatically shown in FIG. 2. Transistors produced in accordance with U.S. Pat. No. 6,492,238 have an epitaxial base layer 101 and a raised outer base portion 102. The emitter 103 is separated from the raised outer base portion 102 by the insulating layer 106 and by an inner spacer layer or spacer 104 and an outer spacer layer 105. A disadvantage of that structure is that the insulation formed by the double spacer 104/105 between the emitter and the raised outer base portion is of its greatest width at the boundary of the epitaxial base layer 101. That structure has been found to be disadvantageous in joint minimisation of base resistance and base-emitter capacitance and accordingly causes restrictions in terms of the high frequency parameters. In addition the choice of the thickness of the insulating layer 106 is limited by the tolerances of the known CMP processes. An excessive thickness of the insulating layer 106 can lead to elevated levels of emitter resistance. In addition the complexity of the production process is substantially increased by the dual application of CMP processes in accordance with U.S. Pat. No. 6,492,238.
(3) EP 0 949 665 A2 discloses a bipolar transistor in which the outer base portion is formed by the diffusion of boron out of a highly doped polysilicon layer into the subjacent monocrystalline silicon. That highly doped polysilicon layer is disposed on an insulating layer in an outward direction. A spacer separates the polysilicon layer from the emitter, which is of an approximately T-shaped configuration. The inner base portion is produced by ion implantation. A disadvantage in regard to the high frequency properties of the transistor structure described therein is on the one hand the great depth of penetration of the diffused-in outer base portion into the monocrystalline layer, as is necessary for a low-ohmic connection of the inner base portion. That increases the base-collector capacitance.